Modern integrated circuits are made up of literally millions of active devices, such as transistors and capacitors. These devices are initially isolated from each other, but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits. On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective chip. Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip bonding. Flip-chip packaging utilizes bumps to establish electrical contact between a chip's I/O pads and the substrate or lead frame of the package. Structurally, a bump actually contains the bump itself and a so-called under-bump-metallurgy (UBM) located between the bump and an I/O pad. An UBM generally contains an adhesion layer, a barrier layer and a wetting layer, arranged in that order, on the I/O pad. The bumps themselves, based on the material used, are classified as solder bumps, gold bumps, copper pillar bumps and bumps with mixed metals. Recently, copper pillar bump technology has been proposed. Instead of using a solder bump, the electronic component is connected to a substrate by means of a copper pillar bump, which achieves finer pitch with minimum probability of bump bridging, reduces the capacitance load for the circuits, and allows the electronic component to perform at higher frequencies.
Copper has a tendency to be oxidized during the manufacturing process. Oxidized copper pillars may lead to poor adhesion of an electronic component to a substrate. The poor adhesion may cause serious reliability concerns due to high leakage currents. Oxidized copper pillars may also lead to underfill cracking along the interface of the underfill and the copper pillars. The cracks may propagate to the underlying low dielectric constant (low-k) dielectric layers or to the solder used to bond the copper pillars to the substrate. A sidewall protection layer is therefore needed to prevent copper oxidation, but the conventional method of processing the Cu pillar sidewall suffers from high process costs and interface delamination issues. Particularly, after a solder joint process, it is observed that the solder material wets onto the exposed sidewall areas of the Cu pillar and under-bump metallurgy (UBM), which causes an intermetallic compound (IMC) to growing during temperature cycling. As the thickness of IMC increases, the solder joint becomes more vulnerable to cracks generated in the solder material. This is a challenge for fine pitch package technology in new generation chips. The current process employs an immersion tin (Sn) process to provide a tin layer on the Cu pillar sidewalls, but there are still concerns regarding process costs, adhesion between Sn and underfill, and issues of solder wetting onto sidewalls.